1. Field of the Invention
The present invention relates to a data processing apparatus and control method thereof.
2. Description of the Related Art
Recent improvement of the degree of semiconductor integration has speeded up a processor and a DRAM often used as a main memory, but the DRAM speed is less increased than the processor speed. To cancel the gap between these speeds, a small-capacity high-speed cache memory is interposed between the high-speed processor and the low-speed main memory.
In most cases, the contents of the main memory are copied to the cache memory only at the time of memory access. However, this method delays processing by the memory latency (time taken to access the memory), decreasing the speed. To hide the memory latency, cache prefetch is performed to copy the contents of the main memory to the cache memory in advance for an address range to be used.
The memory latency can be hidden by performing prefetch as early as possible before fetch for actually performing processing. However, if prefetch is excessively early, data which is prefetched and will be used in the future may be replaced with data to be prefetched.
To solve this problem, in Japanese Patent Laid-Open No. 10-320285, a lock bit is set when storing prefetch data, not to replace prefetched data before read. The lock is released when reading out the locked data. This prevents replacement of data which has been fetched but has not been used even once.
However, in the technique disclosed in Japanese Patent Laid-Open No. 10-320285, when data is used once, the lock is released and the data is subjected to replacement. Even data which is used twice or more after prefetch may be replaced with subsequently prefetched data.